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. U 3 FPGA Data Sheet QL3012 pASIC t4 ee Sh Usable PLD Gate pASIC 3 FPGA Combining High Performance * * * * * a 12,000 t * and High Density a D Highlights Eight Low-Skew Distributed Device . w Networks w Performance & High Density Two array clock/control networks available wHigh Usable PLD Gates with 118 I/Os to the logic cell flip-flop clock, set and reset 12,000
* * * 300 MHz 16-bit Counters,
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400 MHz Datapaths * 0.35 m four-layer metal non-volatile CMOS process for smallest die sizes
Easy to Use / Fast Development Cycles
* 100% routable with 100% utilization and
inputs -- each driven by an input-only pin * Two global clock/control networks available to the logic cell; F1, clock set, reset inputs and the input, I/O register clock, reset, and enable inputs as well as the output enable control -- each driven by an input-only or I/O pin, or any logic cell output or I/O cell feedback
complete pin-out stability * Variable-grain logic cells provide high performance and 100% utilization * Comprehensive design tools include high quality Verilog/VHDL synthesis
Advanced I/O Capabilities
* Interfaces with both 3.3 V and 5.0 V devices * PCI compliant with 3.3 V and 5.0 V buses
for -1/-2/-3/-4 speed grades * Full JTAG boundary scan * I/O Cells with individually controlled Registered Input Path and Output Enables
Total of 118 I/O Pins
* 110 bidirectional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for -1/-2/-3/-4 speed grades * Four High Drive input-only pins * Four High Drive input-only/distributed network pins
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High Performance
* Input + logic cell + output total delays
under 6 ns * Data path speeds over 400 MHz * Counter speeds over 300 MHz
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Figure 1: 320 pASIC 3 Logic Cells
(c) 2003 QuickLogic Corporation
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QL3012 pASIC 3 FPGA Data Sheet Rev F
Architecture Overview
The QL3012 is a 12,000 usable PLD gate member of the pASIC 3 family of FPGAs. pASIC 3 FPGAs are fabricated on a 0.35 m four-layer metal process using QuickLogic's patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use. The QL3012 contains 320 logic cells. With a maximum of 118 I/Os, the QL3012 is available in 84-pin PLCC, 100-pin TQFP, and 144-pin TQFP packages. Software support for the complete pASIC 3 family, including the QL3012, is available through three basic packages. The turnkey QuickWorks package provides the most complete FPGA software solution from design entry to logic synthesis, to place and route, to simulation. The QuickToolsTM for Workstations package provides a solution for designers who use Cadence, ExemplarTM, Mentor, Synopsys, Synplicity, ViewlogicTM, AldecTM, or other third-party tools for design entry, synthesis, or simulation.
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QL3012 pASIC 3 FPGA Data Sheet Rev F
Electrical Specifications
AC Characteristics at VCC = 3.3 V, TA = 25C (K = 1.00)
To calculate delays, multiply the appropriate K factor from Table 7 by the numbers provided in Table 1 through Table 5.
Table 1: Logic Cells Symbol Parameter 1 tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Combinatorial Delay Setup Time b Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width
b
Propagation Delays (ns) Fanouta 2 1.7 1.7 0.0 1.0 1.2 1.2 1.3 1.1 1.9 1.8 3 1.9 1.7 0.0 1.2 1.2 1.2 1.5 1.3 1.9 1.8 4 2.2 1.7 0.0 1.5 1.2 1.2 1.8 1.6 1.9 1.8 8 3.2 1.7 0.0 2.5 1.2 1.2 2.8 2.6 1.9 1.8
1.4 1.7 0.0 0.7 1.2 1.2 1.0 0.8 1.9 1.8
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature settings as specified in Table 7. b. These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.
Table 2: Input-Only/Clock Cells Symbol Parameter 1 tIN tINI tISU tIH tlCLK tlRST tlESU tlEH High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1.5 1.6 3.1 0.0 0.7 0.6 2.3 0.0 Propagation Delays (ns) Fanout a 2 1.6 1.7 3.1 0.0 0.8 0.7 2.3 0.0 3 1.8 1.9 3.1 0.0 1.0 0.9 2.3 0.0 4 1.9 2.0 3.1 0.0 1.1 1.0 2.3 0.0 8 2.4 2.5 3.1 0.0 1.6 1.5 2.3 0.0 12 2.9 3.0 3.1 0.0 2.1 2.0 2.3 0.0 24 4.4 4.5 3.1 0.0 3.6 3.5 2.3 0.0
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature settings as specified in Table 7.
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QL3012 pASIC 3 FPGA Data Sheet Rev F
Table 3: Clock Cells Symbol Parameter Propagation Delays (ns) Loads per Half Column a 1 tACK tGCKP tGCKB Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay 1.2 0.7 0.8 2 1.2 0.7 0.8 3 1.3 0.7 0.9 4 1.3 0.7 0.9 8 1.5 0.7 1.1 10 1.6 0.7 1.2 11 1.7 0.7 1.3
a. The array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to eight loads per half column. The global clock has up to 11 loads per half column.
Table 4: Input-Only I/O Cells Symbol Parameter Propagation Delays (ns) Fanout a 1 tI/O tISU tIH tlOCLK tlORST tlESU tlEH Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1.3 3.1 0.0 0.7 0.6 2.3 0.0 2 1.6 3.1 0.0 1.0 0.9 2.3 0.0 3 1.8 3.1 0.0 1.2 1.1 2.3 0.0 4 2.1 3.1 0.0 1.5 1.4 2.3 0.0 8 3.1 3.1 0.0 2.5 2.4 2.3 0.0 10 3.6 3.1 0.0 3.0 2.9 2.3 0.0
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature settings as specified in Table 7.
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QL3012 pASIC 3 FPGA Data Sheet Rev F
Table 5: Output-Only I/O Cells Symbol Parameter 30 tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State Output Delay Low to Tri-State
a
Propagation Delays (ns) Output Load Capacitance (pF) 50 2.5 2.6 1.7 2.0 75 3.1 3.2 2.2 2.6 100 3.6 3.7 2.8 3.1 150 4.7 4.8 3.9 4.2 -
2.1 2.2 1.2 1.6 2.0 1.2
a. The loads presented in Figure 2 are used for tPXZ:
tPHZ 1 5 pF
1 tPLZ 5 pF
Figure 2: Loads used for tPXZ
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QL3012 pASIC 3 FPGA Data Sheet Rev F
DC Characteristics
The DC specifications are provided in Table 6 through Table 8.
Table 6: Absolute Maximum Ratings Parameter VCC Voltage VCCIO Voltage Input Voltage Latch-up Immunity Value -0.5 V to 4.6 V -0.5 V to 7.0 V -0.5 V to VCCIO +0.5 V 200 mA Parameter DC Input Current ESD Pad Protection Storage Temperature Lead Temperature Value 20 mA 2000 V -65C to +150C 300C
Table 7: Operating Range Symbol Parameter Military Min VCC VCCIO TA TC Supply Voltage I/O Input Tolerance Voltage Ambient Temperature Case Temperature -0 Speed Grade -1 Speed Grade K Delay Factor -2 Speed Grade -3 Speed Grade -4 Speed Grade 3.0 3.0 -55 0.42 0.42 Max 3.6 5.5 125 1.64 1.37 Industrial Min 3.0 3.0 -40 0.43 0.43 0.43 0.43 0.43 Max 3.6 5.5 85 1.90 1.54 1.28 0.90 0.82 Commercial Min 3.0 3.0 0 0.46 0.46 0.46 0.46 0.46 Max 3.6 5.25 70 1.85 1.50 1.25 0.88 0.80 V V C C n/a n/a n/a n/a n/a Unit
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QL3012 pASIC 3 FPGA Data Sheet Rev F
Table 8: DC Characteristics Symbol VIH VIL VOH Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage IOH = -12 mA IOH = -500 A IOL = 16 mAa IOL = 1.5 mA VI = VCCIO or GND VI = VCCIO or GND -10 -10 Conditions Min 0.5 VCC -0.5 2.4 0.9 VCC 0.45 0.1 VCC 10 10 10 VO = GND VO = VCC VI, VIO = VCCIO or GND -15 40 0.50 (typ) 0 -180 210 2 100 Max VCCIO+0.5 0.3 VCC Units V V V V V V A A pF mA mA mA A
VOL II IOZ CI IOS ICC ICCIO
Output LOW Voltage I or I/O Input Leakage Current 3-State Output Leakage Current Input Capacitanceb Output Short Circuit Currentc D.C. Supply Current
d
D.C. Supply Current on VCCIO
a. Applies only to -1/-2/-3/-4 commercial grade devices. These speed grades are also PCI-compliant. All other devices have 8 mA IOL specifications. b. Capacitance is sample tested only. Clock pins are 12 pF maximum. c. Only one output at a time. Duration should not exceed 30 seconds. d. For -1/-2/-3/-4 commercial grade devices only. Maximum ICC is 3 mA for -0 commercial grade and all industrial grade devices, and 5 mA for all military grade devices. For AC conditions, contact QuickLogic customer applications group (see "Contact Information" on page 16).
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QL3012 pASIC 3 FPGA Data Sheet Rev F
Kv and Kt Graphs
Voltage Factor vs. Supply Voltage
1.1000 1.0800 1.0600 1.0400
Kv
1.0200 1.0000 0.9800 0.9600 0.9400 0.9200 3 3.1 3.2 3.3 3.4 3.5 3.6
Supply Voltage (V)
Figure 3: Voltage Factor vs. Supply Voltage
Temperature Factor vs. Operating Temperature
1.15 1.10 1.05 1.00 0.95 0.90 0.85 -60 -40 -20 0 20 40 60 80
Kt
Junction Temperature C
Figure 4: Temperature Factor vs. Operating Temperature
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QL3012 pASIC 3 FPGA Data Sheet Rev F
Power-up Sequencing
VCCIO
Voltage
VCC (VCCIO -VCC)MAX VCC
400 us
Time
Figure 5: Power-up Requirements
When powering up a device, the VCC/VCCIO rails must take 400 s or longer to reach the maximum value (refer to Figure 5). NOTE: Ramping VCC/VCCIO to the maximum voltage faster than 400 s can cause the device to behave improperly. For users with a limited power budget, keep (VCCIO -VCC)MAX 500 mV when ramping up the power supply.
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QL3012 pASIC 3 FPGA Data Sheet Rev F
JTAG
TCK TMS TRSTB TAp Controller State Machine (16 States) Instruction Decode & Control Logic
Instruction Register
RDI
Mux Boundary-Scan Register (Data Register)
Mux
TDO
Bypass Register
Internal Register
I/O Registers
User Defined Data Register
Figure 6: JTAG Block Diagram
Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, not the least of which concerns the accessibility of test points. The Joint Test Access Group (JTAG) formed in response to this challenge, resulting in IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan Architecture. The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port (TAP) controller works in concert with the Instruction Register (IR); these allow users to run three required tests, along with several user-defined tests. JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements.
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QL3012 pASIC 3 FPGA Data Sheet Rev F
The 1149.1 standard requires the following three tests:
* Extest Instruction. The Extest instruction performs a PCB interconnect test. This test
places a device into an external boundary test mode, selecting the boundary scan register to be connected between the TAP's Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are preloaded with test patterns (via the Sample/Preload Instruction), and input boundary cells capture the input data for analysis. * Sample/Preload Instruction. This instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the functional data entering and leaving the device. * Bypass Instruction. The Bypass instruction allows data to skip a device's boundary scan entirely, so the data passes through the bypass register. The Bypass instruction allows users to test a device without passing through other devices. The bypass register is connected between the TDI and TDO pins, allowing serial data to be transferred through a device without affecting the operation of the device.
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QL3012 pASIC 3 FPGA Data Sheet Rev F
Pin Descriptions
Table 9: Pin Descriptions Pin TDI TRSTB TMS TCK TDO STM I/ACLK I/GCLK I I/O VCC VCCIO GND Function Test Data In for JTAG Active low Reset for JTAG Test Mode Select for JTAG Test Clock for JTAG Test data out for JTAG Special Test Mode Description Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold LOW during normal operation. Connect to ground if not used for JTAG. Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold HIGH or LOW during normal operation. Connect to VCC or ground if not used for JTAG. Output that must be left unconnected if not used for JTAG. Must be grounded during normal operation.
High-drive input and/or array Can be configured as either or both. network driver High-drive input and/or global Can be configured as either or both. network driver High-drive input Input/Output pin Power supply pin Input voltage tolerance pin Ground pin Use for input signals with high fanout. Can be configured as an input and/or output. Connect to 3.3 V supply. Connect to 5.0 V supply if 5 V input tolerance is required, otherwise connect to 3.3 V supply. Connect to ground.
Ordering Information
QL 3012 - 1 PQ208 C QuickLogic device pASIC 3 device part number Speed Grade 0 = Quick 1 = Fast 2 = Faster 3 = Faster *4 = Wow Operating Range C = Commercial I = Industrial M = Military Package Code PL84 = 84-pin PLCC PF100 = 100-pin TQFP PF144 = 144-pin TQFP
* Contact QuickLogic regarding availability (see "Contact Information" on page 16).
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QL3012 pASIC 3 FPGA Data Sheet Rev F
84 PLCC Pinout Diagram
11 10 9 87 65 43 2 1 84 83 82 81 80 79 78 77 76 75
TDO IO IO IO IO IO IO VCCIO IO IO IO IO IO GND IO IO VCC IO IO STM TCK
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
84 PLCC Pinout Diagram
Table 10: 84 PLCC Pinout Diagram
84 PLCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function
I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O TDO I/O I/O I/O I/O I/O I/O I/O GND I/O I
TDI IO IO VCC IO IO IO GND IO IO IO IO IO VCCIO IO IO IO IO IO TRSTB TMS
IO IO IO IO IO IO IO GND IO I ACLK/I I GCLK/I VCC IO IO IO IO IO IO IO
pASIC 3 QL3012-1PL84C
IO IO IO IO IO IO IO VCC GCLK/I I ACLK/I I IO GND IO IO IO IO IO IO IO
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
Figure 7: Top View of 84 Pin PLCC
84 PLCC 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Function
ACLK/I I GCLK/I VCC I/O I/O I/O I/O I/O I/O I/O TDI I/O I/O VCC I/O I/O I/O GND I/O I/O
84 PLCC 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Function
I/O I/O I/O VCCIO I/O I/O I/O I/O I/O TRSTB TMS I/O I/O I/O I/O I/O I/O I/O GND I/O I
84 PLCC 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
Function
ACLK/I I GCLK/I VCC I/O I/O I/O I/O I/O I/O I/O TCK STM I/O I/O VCC I/O I/O GND I/O I/O
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QL3012 pASIC 3 FPGA Data Sheet Rev F
100 TQFP Pinout Diagram
Pin 1 Pin 76
pASIC 3 QL3012-1PF100C
Pin 26
Pin 51
Figure 8: Top View of 100 Pin TQFP
144 TQFP Pinout Diagram
Pin 109
Pin 1
pASIC 3 QL3012-1PF144C
Pin 37
Pin 73
Figure 9: Top View of 144 Pin TQFP
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QL3012 pASIC 3 FPGA Data Sheet Rev F
100 & 144 TQFP Pinout Table
Table 11: 100 & 144 TQFP Pinout Table
144 TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 100 TQFP 2 3 NC 4 NC 5 NC 6 NC 7 NC NC 8 NC 9 10 11 12 13 14 15 16 17 18 NC 19 NC 20 21 NC NC 22 23 NC NC 24 25 Function
I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O GND I/O I ACLK / I VCC I GCLK / I VCC I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O
144 TQFP 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74
100 TQFP 26 27 28 29 NC 30 31 NC 32 33 NC 34 35 36 NC 37 38 39 40 41 42 NC 43 44 45 NC NC 46 NC NC NC 47 48 49 50 51 52
Function
TDI I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O GND I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O TRSTB TMS I/O I/O
144 TQFP 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 NC 97 98 99 100 101 102 103 104 105 106 107 108 109 110
100 TQFP 53 54 55 NC NC NC 56 NC 57 NC 58 NC 59 60 61 62 63 64 65 66 67 NC 68 NC 69 NC 70 71 NC NC 72 NC 73 74 75 76 77
Function
I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O GND I/O I ACLK / I VCC I GCLK / I VCC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O TCK STM
144 TQFP
111
100 TQFP
78
Function
I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O GND I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O TDO I/O
112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 NC 137 138 139 140 141 142 143 144
79 80 NC 81 82 83 NC 84 NC NC 85 NC 86 87 88 89 90 91 92 NC 93 NC 94 NC NC 95 NC NC 96 97 98 99 100 1
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QL3012 pASIC 3 FPGA Data Sheet Rev F
Contact Information
Telephone: (408) 990 4000 (US) (416) 497 8884 (Canada) +(44) 1932 57 9011 (Rest of Europe) +(49) 89 930 86 170 (Germany & Benelux) +(8621) 2890 3029 (Asia) +(81) 45 470 5525 (Japan) E-mail: Support: Web site: info@quicklogic.com http://www.quicklogic.com/support http://www.quicklogic.com/
Revision History
Table 12: Revision History Revision A B C D E F Date not avail. not avail. not avail May 2001 June 2002 July 2003 Update of AC/DC Specs and reformat Added Kfactor, Power-up, JTAG and mechanical drawing information. Reformatted. Updated text section in Power-up Sequencing and Contact information. Comments First release.
Copyright Information
Copyright (c) 2003 QuickLogic Corporation. All Rights Reserved. The information contained in this product brief, and the accompanying software programs are protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to make periodic modifications of this product without obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited. QuickLogic, QuickWorks, pASIC, and ViaLink are registered trademarks of QuickLogic Corporation. Verilog is a registered trademark of Cadence Design Systems, Inc. All trademarks and registered trademarks are the property of their respective owners.
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